The present invention relates generally to a MIS (Metal-Insulator-Semiconductor) dynamic random access memory and, more particularly, to an active pull-up circuit for use in a sense amplifier, a word decoder or the like.
In general, a MOS (broadly, MIS) dynamic memory device of a one-transistor and one-capacitor type incorporates memory cells, each comprising a capacitor and an enhancement type transistor which serves as a switching gate for charging or discharging the capacitor. In this case, the presence or absence of charges corresponds to the data "0" or "1." Such memory cells are arranged at intersections between word lines and bit line pairs. In addition, dummy memory cells, which are similar in structure to the memory cells, are arranged at intersections between dummy word lines and the bit line pairs.
In the above-mentioned memory device, a sense amplifier is provided for each bit line pair, in order to read memory information. Therefore, when a memory cell is selected, so that a small difference in potential is generated between the bit line pair connected to the selected memory cell, the sense amplifier senses or enlarges the small difference in potential by pulling down the low-level side potential of the bit line pair. As a result, a large difference in potential is obtained between the bit line pair. This large difference is helpful in the read operation. However, it should be noted that, even in this case, the high-level side potential of the bit line pair is also decreased slightly due to the capacity coupling of the bit line, leak currents and the like, thereby deteriorating the sensing speed of the sense amplifier. To avoid this, the high-level potential is again pulled up by an active pull-up circuit.
A first conventional active pull-up circuit for use in a sense amplifier comprises: a first enhancement type MIS transistor having a drain connected to a power supply (V.sub.cc) and a source connected to a bit line; a MIS capacitor having an electrode for receiving a first clock signal and another electrode connected to the gate of the first enhancement type transistor; and a second enhancement type MIS transistor having a drain connected to the gate of the first enhancement type transistor, a source connected to the bit line and a gate receiving a second clock signal (See: Digest of Technical Papers of 1980 IEEE International Solid-State Circuits Conference, pp. 230-231, FIG. 1). In this case, the potential of the first clock signal is low (V.sub.ss) and high (V.sub.cc) during the stand-by mode and the pull-up mode, respectively. On the other hand, the potential of the second clock signal is high (&gt;V.sub.cc +V.sub.th) and low (V.sub.cc) during the stand-by mode and the pull-up mode, respectively. Here, V.sub.th is a common threshold voltage of the first and second enhancement type transistors.
However, in the above-mentioned first conventional circuit, it is difficult to generate the second clock signal having a high potential which is higher than V.sub.cc +V.sub.th, since another power supply or a bootstrap circuit is required for generating such a high potential.
A second conventional active pull-up circuit comprises a depletion type MIS transistor instead of the second enhancement type MIS transistor of the first conventional circuit. In this case, it should be noted that the gate of the depletion type transistor is connected to a power supply (V.sub.ss) or to ground (See: Digest of Technical Papers of 1979 IEEE International Solid-State Circuits Conference, pp. 142-143, FIG. 1). Therefore, this circuit has an advantage in that a clock signal whose potential is very high (&gt;V.sub.cc +V.sub.th) is unnecessary.
However, the second conventional circuit has a disadvantage in that a selection range for the negative threshold voltage V.sub.th (d) of the depletion type transistor is so small that it is difficult to manufacture a semiconductor device including such active pull-up circuits. This is because the potential of the gate of the first enhancement type transistor is at most .vertline.V.sub.th (d).vertline. during the stand-by mode, which requires a large bootstrap effect due to the active pull-up circuit and, accordingly, requires a large capacity of the MIS capacitor. Therefore, the value of .vertline.V.sub.th (d).vertline. is preferably as large as possible. On the other hand, the potential of the high-level bit line prior to the pull-up mode must be higher than .vertline.V.sub.th (d).vertline., in order to cause the bootstrap effect of the active pull-up circuit. Therefore, the value of .vertline.V.sub.th (d).vertline. is preferably as small as possible, which is, however, contradictory to the above.